When a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is scaled down through various technology nodes, high-k gate dielectric layer and metal gate electrode layer are incorporated into the gate stack of the MOSFET to improve device performance with the decreased feature sizes. The MOSFET processes comprise a “gate last” process to replace an original poly-silicon gate electrode with the metal gate electrode to improve device performance.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, it is difficult to prevent parasitic capacitance among gate stacks of the MOSFET because of the reduced spacing between the gate stacks, thereby affecting the device performance.
Accordingly, what is needed is an improved method for fabricating the gate stacks in a semiconductor device.